Regviz

NXP Semiconductors /MIMXRT1062 /XTALOSC24M /OSC_CONFIG2_SET

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OSC_CONFIG2_SET

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1062/XTALOSC24M/OSC_CONFIG2_SET#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0COUNT_1M_TRG0 (ENABLE_1M)ENABLE_1M 0 (MUX_1M)MUX_1M 0 (CLK_1M_ERR_FL)CLK_1M_ERR_FL

Description

XTAL OSC Configuration 2 Register

Fields

COUNT_1M_TRG

The target count used to tune the 1MHz clock frequency
ENABLE_1M

Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
MUX_1M

Mux the corrected or uncorrected 1MHz clock to the output
CLK_1M_ERR_FL

Flag indicates that the count_1m count wasn’t reached within 1 32kHz period

Links

()

Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data